An integrated circuit (LSI; Large-Scale Integrated circuit) is designed in an RTL (Register Transfer Level) using a hardware description language. Design information on the LSI described in the RTL and a property expressing a specification of the LSI described in a specification description language are compared by using a verification tool. The verification tool verifies equivalence between the design information and the property.
An LSI includes a circuit structure having plural RTLs of the same type (hereinafter, referred to as one-type-N-sheets structure), where N is an integer. In order to generate a property of such an LSI, a large number of descriptions having similar patterns are necessary. For example, even when a property is generated for a structure corresponding to a single sheet of the one-type-N-sheets structure of the LSI, a large number of descriptions having similar patterns are needed. Accordingly, generating the property for the one-type-N-sheets structure as a whole needs a huge amount of work.
Reducing the work for generating such a property is desired.
Technologies of related arts with respect to the RTL and the property will be described below.
Japanese Patent Application Laid-Open No. 2003-85221 discloses an RTL automatic classification system. The RTL automatic classification system includes RTL analyzing means and RTL output means. The RTL analyzing means generates input/output signal information, for each of at least one logic descriptions written in a first RTL module. The RTL output means converts each logic description into a hierarchy instance, which includes the input/output signal information on each logic description. The RTL output means further converts the first RTL module into a second RTL module, which is hierarchized by hierarchy instances.
Japanese Patent Application Laid-Open No. 2006-293891 discloses a property converting apparatus. The property converting apparatus converts property information, which describes a specification of hardware in a specification description language, into a logically equivalent expression. The property converting apparatus includes syntax information storage means, syntax analysis means and property equivalent conversion means. The syntax information storage means stores property structural unit information including: a structural unit, of which the property information is composed; order of conversion for the structural units in the equivalent transformation; and an expression logically equivalent to the structural unit. The syntax analysis means generates syntax element information, with reference to the property information, which describes an inputted specification of hardware in the specification description language, and to the property structural unit information stored in the syntax information storage means. The syntax element information includes grammatical structure, a structural unit and an expression equivalent to each structural unit. The property equivalent conversion means creates equivalent property information converted from property information of the inputted hardware into a predetermined equivalent expression, based on the syntax element information.
Japanese Patent Application Laid-Open No. 2002-182926 discloses a compilation method, which generates an object code of fixed length instructions from a source program. The compilation method includes a step for detecting an instruction of grouping for variables irrelevant to each other as a whole in a source program, a step for, when the instruction of grouping is detected, grouping the variables based on the instruction of grouping, a step for detecting a reference position of the grouped variables from the source program, and a step for generating the object code for the detected reference position of the variables. The object code appends an offset address of a variable to a base address common to a group, to which the variable belongs, and refers to the variable.
Japanese Patent Application Laid-Open No. 2003-6256 discloses a high level synthesizer unit for a logic circuit. The high level synthesizer unit of the logic circuit performs synthesizes to generate a logic circuit based on action descriptions. The high level synthesizer unit includes an array variable analysis unit and a variable rewriting unit. The array variable analysis unit analyzes an array variable in inputted action descriptions, and generates array variable analysis data, which includes a virtual name assigned to an element of the array, according to a variable name and addresses of elements of the array. The variable rewriting unit generates after-rewriting action descriptions from the action descriptions based on the array variable analysis data. The high level synthesizer unit performs high level synthesis processes for the logic circuit based on the after-rewriting action descriptions.
Japanese Patent Application Laid-Open No. 2006-252438 discloses a verification support apparatus. The verification support apparatus is provided with a semiconductor package. The verification support apparatus includes input means, designation means and detection means. The input means receives input of logic circuit description information on a verification object. The designation means designates, in the verification object, two or more registers, each of which outputs data from one clock domain of a pair of neighboring clock domains. The detection means detects a single register, which converges in the other clock domain (re-convergent register) based on the logic circuit description information on the verification object inputted by the input means, and on two or more registers designated by the designation means.